Stochastic cycle period analysis in timed circuits

This paper presents a method of deriving a performance metric for timed asynchronous circuits called a stochastic cycle period, which uses analytical techniques combined with simulation to capture the stochastic profile of the system. The stochastic cycle period is constructed by finding transition and steady-state probabilities in a reachability graph of the timed circuit. The transition and steady-state probabilities are used to obtain trigger probabilities in the circuit implementation. The trigger probabilities are then used in a timing simulation to construct the stochastic cycle period of the timed specification. Since this performance metric is a stochastic profile of the circuit behavior with regards to its individual components, synthesis optimization efforts can be focused on areas that significantly improve the expected cost of a cycle in the system. This paper presents some case studies where the metric is used to evaluate and improve designs. The studies show the potential of the performance metric and its import in the design process.